1. Technical Field
The present invention relates generally to memory circuit design methodologies and programs for designing digital memory circuits, and more particularly to a method and computer program for improving static memory performance across process variations and environmental conditions.
2. Description of the Related Art
Memory speed and other performance factors are critical limitations in today's processing systems and are predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memories (SRAMS) and memory cells are used in processor caches, registers and in some designs external to the system processors for fast access to data and program instructions.
With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, at process scales necessary to achieve such access are also increasingly subject to variability in circuit parameters such as device threshold voltages and channel dimensions. Charge history effect and physical nano-scale effects due to non-ideal materials also come increasingly into place as device size is decreased.
Semiconductor memories in general are also becoming the predominant power consumer in almost every processing system and particularly in processors, cache memory is a major consumer of power. As such, reduction of SRAM cell power supply voltages is highly desirable, as power dissipation and overall power requirements are dictated by the supply voltages used. However, lower supply voltages typical dictate lower performance levels in terms of cell read and write stability and access delay.
Because of all of the above-described limitations, yield reduction due to SRAM cell variability or increased redundancy requirements will increase production cost and waste or limit available space and design flexibility in order to provide sufficient redundancy to maintain yields.
Present analysis techniques require large amounts of processing power to extend an accurate yield/performance analysis beyond three standard deviations (3σ) of device parameter variations. However, if it were practical to perform more extensive analyses and further if a technique for determining which design parameters can be efficaciously altered were provided, memory device designs could be improved beyond present levels and designs for much higher operating frequencies could be generated.
It is therefore desirable to provide a method for modeling and improving SRAM cell performance across process variations and environmental operating conditions in an efficient manner so that device parameter variations can be simulated to a level of 5σ and beyond.